As an integration of a semiconductor device goes on, a research on a capability enhancement of the semiconductor device as well as down sizing thereof is performed at the same time. At present, most wiring structure of the semiconductor device adopts a multi-layer wiring structure. The multi-layer wiring structure may overcome problems on signal transmission speed that are generated during an operation of highly integrated device. And with an advent of the multi-layer wiring structure, a dual damascene process is highlighted due to its simplicity. The dual damascene process is composed of the steps of forming a contact hole and a trench in an insulating layer, performing a gap-fill on a conductive film, and performing a chemical mechanical polishing to thereby form a wiring and a contact hole at the same time.
There are several methods for forming a dual damascene structure in a semiconductor device. One of a conventional methods is shown in FIGS. 1A to 1D. Two photolithographic processes and two insulator layers separated by an etch stop layer are employed to achieve the shown structure as follows. In this method, the dual damascene structure is formed by a way that a trench is first formed and then a contact hole is formed in an insulating layer later.
As shown in FIG. 1A, a semiconductor substrate 10 is provided with a semiconductor device (not shown) therein. Thereafter, a first etch stop layer 12 is applied on the semiconductor substrate 10. And then, a first insulating layer 14, a second etch stop layer 16 and a second insulating layer 18 are deposited on the first etch stop layer 12 sequentially. And then, a first photoresist pattern 20 for defining the trench is formed on the second insulating layer 18 by a photolithography process.
And, as shown in FIG. 1B, the second insulating layer 18, in turn, is etched down to the second etch stop layer 16 so that a trench 18a is formed and then the first photoresist pattern layer 20 is removed.
And then, as shown in FIG. 1C, a second photoresist layer 22 for defining a contact hole 24 is applied on the trench 18a. 
Thereafter, as shown in FIG. 1D, the second etch stop layer 16 and the first insulating layer 14 defined by the second photoresist pattern 22 is etched so that the contact hole 24 can be formed. In another embodiment, the first etch stop layer 12 may also be etched down to expose a portion of the semiconductor device, such as a wiring or an activated area, although it is not shown in FIG. 1D. Thereafter, the second photoresist pattern 22 is removed to complete a dual damascene structure.
Another conventional method for forming a dual damascene structure is presented in FIGS. 2A to 2D, in which a contact hole is first formed in an insulating layer and then a trench is formed.
As described in FIG. 2A, a semiconductor substrate 30 is provided with a semiconductor device therein. Thereafter, a first etch stop layer 32 is applied on the semiconductor substrate 30. And then, a first insulating layer 34, a second etch stop layer 36 and a second insulating layer 38 are deposited on the first etch stop layer 32 sequentially. And then, a first photoresist pattern 40 for defining a contact hole is formed on the second insulating layer 38 by a photolithography process.
And, as shown in FIG. 2B, the second insulating layer 38, the second etch stop layer 36 and the first insulating layer 34 are etched down so that a contact hole 42 is formed. And then the first photoresist pattern layer 40 is removed. In another embodiment, though it is not shown in FIG. 2B, the contact hole 42 uncovering a portion of a semiconductor device may formed by etching the first etch stop layer 32.
And then, as shown in FIG. 2C, a second photoresist layer 44 for defining a trench 48 is applied on the second insulating layer 38a. At this time, a gap filler 46 for filling the contact hole 42 up to the second etch stop layer 36a is formed in order to protect the semiconductor device when the second insulating layer 38a is etched.
Thereafter, as shown in FIG. 2D, the second insulating layer 38a defined by the second photoresist pattern 44 is etched to form the trench 48 for wiring. Then, the second photoresist pattern 44 and the gap filler 46 are removed to complete the dual damascene structure.
Still another conventional method for forming a dual damascene structure is shown in FIGS. 3A to 3D. In this method, the dual damascene structure is formed by a way that a trench for wiring and a contact hole are formed by a self-aligned process.
As described in FIG. 3A, a semiconductor substrate 50 is provided with a semiconductor device therein. Thereafter, a first etch stop layer 52 is applied on the semiconductor substrate 50. And then, a first insulating layer 54 and a second etch stop layer 56 are deposited on the first etch stop layer 52 sequentially. And then, a first photoresist pattern 58 for defining a contact hole is formed on the second etch stop layer 52 by a photolithography process.
And, as shown in FIG. 3B, the second etch stop layer 56, in turn, is etched to form a patterned second etch stop layer 56a and then the first photoresist pattern layer 58 is removed.
Sequentially, as shown in FIG. 3C, a second insulating layer 60 is applied on the structure of FIG. 3B and a second photoresist layer 62 for defining the trench for wiring is applied on the second insulating layer 60.
And then, as shown in FIG. 3D, the second insulating layer 60 defined by the second photoresist pattern 62 is etched and at the same time the first insulating layer 54 also is etched by using the patterned second etch stop layer 56a in a self-aligned way to form a dual damascene contact hole 64. Thereafter, the second photoresist pattern 62 is removed to complete the dual damascene structure. In another embodiment, though it is not shown in FIG. 3D, the first etch stop layer 52 may be etched so as for the underlying semiconductor device to be exposed.
Therefore, it is evident that the process is complicated, especially in that two photoresist processes must be used to form the trench and contact hole patterns. The multiplicity of the processes results in a lower productivity, and an increased cost.